On-Chip ECC for Low-Power SRAM Design
نویسنده
چکیده
As the standby supply voltage for the static RAM (SRAM) design scales down for the low-power purpose, the static noise margin of SRAM also decreases. If the supply voltage is below the data retention voltage (DRV), the data need to be checked and corrected before they are sent out of the memory block. In this project, we study the effect of implemented error correction code (ECC) technique to the SRAM design. The performance is evaluated in both model simulation and circuit performance perspective.
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